1. Field of the Invention
The invention relates to a thin film transistor with photoconductive material. More particularly, the invention reduces the parasitic capacitance between the source and gate, increases the clear aperture of each pixel, and eliminates flicker and feed-through voltage by providing a thin film transistor with photoconductive material.
2. Description of the Related Art
FIG. 1A is a top view schematically showing a pixel of a liquid crystal display in the prior art. As shown in FIG. 1A, the liquid crystal pixel 1 has an aperture 10, a gate line 20 adjacent to one side of the aperture 10, and a data line 30 adjacent to another side of the aperture 10. The liquid crystal material is confined in the aperture 10, and the gate line 20 has a thin film transistor 40 for controlling the liquid crystal whether the light passes through it or not. FIG. 1B schematically shows a cross-section of the thin film transistor taken along the line A-Axe2x80x2 of FIG. 1A. As shown in FIG. 1B, a metal gate layer 402 is formed on a transparent substrate 401, such as glass (e.g., Corning 1737, from Corning Glass, Japan) by sputter deposition, standard lithographic techniques and dry etching. The metal gate layer 402 is opaque to light in the thin film transistor structure. A dielectric layer 403 is formed on the metal gate layer 402 and the substrate 401, and then an amorphous Si layer 404 is formed on the dielectric layer 403. A source electrode 406 is formed on the amorphous Si layer 404 and the dielectric layer 403 over one side of the metal gate layer 402, and a drain electrode 407 is also formed on the amorphous Si layer 404 and the dielectric layer 403 over another side of the metal gate layer 402. Thus, the thin film transistor (TFT) has a channel 408 formed between source 406 and drain electrodes 407. A passivation layer 405 is next formed on the dielectric layer 403, source electrode 406, drain electrode 407, and amorphous layer 404. In FIG. 1B, the drain electrode 407 overlaps the metal gate layer 402 to form a drain overlap 409a, and the source electrode 406 overlaps the metal gate layer 402 to form a source overlap 409b. Thus, the source overlap 409b conducts electricity between the source electrode 406 and metal gate layer 402, and the drain overlap 409a conducts electricity between the drain electrode 407 and metal gate layer 402. However, the parasitic capacitance is established between the source/drain electrode and the metal gate layer where they overlap one another. FIG. 1C schematically shows an equivalent circuit of the liquid crystal pixel having the parasitic capacitance. Each liquid crystal pixel 50 is provided with TFT 52, which acts as a switch for addressing the liquid crystal pixel. The gate electrode 54 of TFT 52 is connected to gate line 60, and the source electrode 56 of TFT 52 is connected to data line 62. The drain electrode 58 of TFT 52 is connected to a display element 66, such as a liquid crystal pixel. FIG. 1D illustrates a number of the disadvantageous consequences of parasitic capacitance and feed-through voltage. At time t1, the voltage on data line 62 is high, but the voltage on gate line 60 is low. Consequently, voltage is not permitted to flow between data line 62 and pixel 66, and the pixel is opaque or OFF. At time t2, the voltage on data line 62 remains high, but the voltage on gate line 60 goes from low to high (typically 10-20 volts). The channel of TFT 52 is consequently opened. This results in application of voltage from data line 62 to pixel 66, causing pixel 66 to become transparent or ON. Pixel 66 typically has a certain degree of inherent capacitance, shown as Cpix. Also, due to the architecture of an integrated TFT, there typically is an overlap between the drain electrode 58 of the TFT 52 and gate electrode 54. This results in a capacitance Cgd between the drain and gate. Thus, between time t2 and time t3, voltage at pixel 66 is as intended. At time t3, the voltage on gate line 60 is switched to low. Charge in the channel of TFT 52 is thereby depleted. However, at this time there is a difference in potential across Cgd, which causes part of the charge stored in Cpix to be redistributed to Cgd, resulting in a voltage drop, xcex94Vp, referred to as feed-through voltage. In the case of a display apparatus, the feed-through voltage results in aforementioned image xe2x80x9cflickerxe2x80x9d. At time t4, voltage on the data line 62 is low, and the voltage on gate line 60 is switched from low to high. This once again opens the channel of TFT 52, and the capacitance Cpix is discharged to the line level of data line 62, switching pixel 66 OFF. AT time t5, voltages on both the gate line 60 and the data line 62 are low. However, again there is a difference in potential across Cgd, which results in another feed-through voltage drop. The drop voltage is represented as
xcex94Vp=[Cgd/(Cpix+Cgd)]xc3x97xcex94Vg,
wherein Cpix is the inherent capacitance of the liquid crystal pixel, and Cgd is a parasitic capacitance between the drain and gate.
Another prior art provides a storage capacitance for reducing the influence of parasitic capacitance on pixel voltage and eliminating the flicker. As shown in FIG. 2A, each pixel provides a storage capacitance 70 at respective aperture 10. However, the storage capacitance occupies partial aperture of the pixel and reduces the brightness of the liquid crystal display. FIG. 2B schematically shows an equivalent circuit of the liquid crystal pixel having the storage capacitance. In FIG. 2B, each pixel has a drop voltage, and the drop voltage is represented as
xcex94Vp=[Cgd/(Cst+Cpix+Cgd)]xc3x97xcex94Vg,
wherein Cpix is the inherent capacitance of the liquid crystal pixel, Cgd is a parasitic capacitance between the drain and gate, and Cst is the storage capacitance. As the Cst is increased, the drop voltage xcex94Vp caused by the parasitic capacitance is decreased. However, as the parasitic capacitance is larger, the clear aperture of each pixel is smaller and the brightness of the liquid crystal display is lower.
Moreover, each liquid crystal panel is divided into several regions, and then each region forms a plurality of pixels by photolithography. The pixels in respective regions are slightly dissimilar. Further, the dimensions of the drain overlap and source overlap in each TFT are also slightly dissimilar, and the phenomenon results in different parasitic capacitance in respective pixels, and the liquid crystal display shows Shot Mura on screen.
To solve the above problems, it is an object of the present invention to provide a liquid crystal display of thin film transistor with photoconductive material. When light illuminates the photoconductive material, a current/signal is conducted between the drain electrode and gate electrode. When light is blocked from illuminating the photoconductive material, it is insulated between the drain and gate. The invention further reduces the parasitic capacitance between the drain and gate.
The invention has an advantage of reducing or eliminating the parasitic capacitance and feed-through voltage by providing photoconductive material between the drain electrode and gate electrode.
The invention has another advantage of increasing the brightness of the liquid crystal display by forming individual pixels without storage capacitance.
The invention has another advantage of reducing or eliminating the flicker and Shot Mura by forming a photoconductive layer between the drain electrode and gate.